Clarke (t.clark) - Spring Term 2003 (All Weeks)
Date Produced: 29 January 2004
2004 Spring Term Timetable
Time
Monday
Tuesday
Wednesday
Thursday
Friday
09:00
10:00
VHDL & Logic Synthesis
LEC (1-11) / i3 / EE508
VHDL & Logic Synthesis
LEC (1-11) / i3 / EE408
11:00
12:00
13:00
14:00
15:00
16:00
17:00