Advanced Computer Architecture

Lecturer : Paul Kelly (homepage)
For course notes click on the lecturers homepages.

This a third-level course, that aims to develop a thorough understanding of high-performance and energy-efficient computer architecture, as a basis for informed software performance engineering and as a foundation for advanced work in computer architecture, compiler design, operating systems and parallel processing.

Topics include:

* Pipelined CPU architecture. Instruction set design and pipeline structure. Dynamic scheduling using scoreboarding and Tomasulo's algorithm; register renaming. Software instruction scheduling and software pipelining. Superscalar and long-instruction-word architectures (VLIW, EPIC and Itanium). Branch prediction and speculative execution.
Simultaneous multithreading ('hyperthreading'), and vector instruction sets (such as SSE and AVX).

* Caches: associativity, allocation and replacement policies, sub-block placement. Multilevel caches, multilevel inclusion. Cache performance issues. Uniprocessor cache coherency issues: self-modifying code, peripherals, address translation.

* Dependence in loop-based programs; dependence analysis, and iteration-space transformations - to enable automatic parallelisation, vectorisation (eg for SSE), and for memory hierarchy optimisations such as tiling.

* Implementations of shared memory: the cache coherency problem. Update vs invalidation. The bus-based 'snooping' protocol design space.
Scalable shared memory using directory-based cache coherency. How shared memory supports programmability; OpenMP and MPI.

* Graphics processors and 'manycore' architectures: SIMT ('single instruction multiple thread), and the CUDA and OpenCL programming models. Decoupling, latency tolerance, throughput-intensive memory system architecture.

Further details are available from the course web site, http://www.doc.ic.ac.uk/~phjk/AdvancedCompArchitecture.html