FloatWatch

We present a methodology for generating floating-point arithmetic hardware designs which are, for suitable applications, dramatically reduced in size, while still retaining performance and IEEE-754 compliance. Our system uses three key parts: a profiling tool, customisable floating-point units and a selection of system integration methods.

We use a profiling tool for floating-point behaviour to identify arithmetic operations where fundamental elements of IEEE-754 floating-point may be compromised, without becoming non-compliant in the common case. In particular, we identify from input operands the shift amounts required for input operand alignment and post-operation normalisation. For operations where these are small, we synthesis hardware with reduced-size barrel-shifters, but always detect when operands lie outside the range this optimised hardware can handle. We also propose optimisations to take advantage of other profile-exposed behaviours, such as reducing the hardware required to swap operands in a floating-point adder or subtractor. Out-of-range operations are handled by a separate full floating-point implementation, either on-chip or by returning calculations to a host processor, for which we present methods of system integration. Thus the system suffers no compromise in IEEE754 compliance, even when the synthesised hardware would generate erroneous results.

We present profiling results for a range of applications, including real scientific code, Spec FP 95 benchmarks and the FFMPEG media processing tool, indicating which would be amenable to our method. Selected applications which demonstrate potential for optimisation are then taken through to a hardware implementation. We show up to a 45% decrease in hardware size for a floating-point datapath, with a correctable error-rate of less than 3%, even with non-profiled datasets.

• "Speculative Reduction of Floating Point Datapaths" (Extended paper from HiPEAC workshop)
  

Hipeac Workshop on Reconfigurable Computing 2008

• "Profile-directed speculative optimization of reconfigurable floating point data paths", Workshop on Reconfigurable Computing at HiPEAC 2008, Gothenburg, Sweden
  
• Workshop Presentation
  

3rd Computer Systems Research Day, London, September 2007

• Research Day Poster (2nd Prize)
  
• Research Day Slide
  

Transfer, June 2007

• Transfer Presentation
  
• MPhil to PhD Transfer Report, June 2007
  

Hipeac Workshop on Reconfigurable Computing

• "Profiling floating point value ranges for reconfigurable implementation", Workshop on Reconfigurable Computing at HiPEAC 2007, Ghent, Belgium
  
• Workshop Presentation