Shudu Lake, Yunnan

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Publications

[1] Thomas C.P. Chau, Wayne Luk, Alison Eele and Jan Maciejowski, "Adaptive Sequential Monte Carlo Approach for Real-time Applications," submitted to International Conference on Field Programmable Logic and Applications (FPL).

[2] Alison Eele, Jan Maciejowski, Thomas C.P. Chau and Wayne Luk, "Parallelisation of Sequential Monte Carlo for Control in Air Traffic Management," submitted to IEEE Conference on Decision and Control (CDC).

[3] Thomas C.P. Chau, Wayne Luk and Peter Y.K. Cheung, "Roberts: Reconfigurable Platform for Benchmarking Real-time Systems," to appear in ACM SIGARCH Computer Architecture News.

[4] Man-Ho Ho, Yan-Qing Ai, Thomas C.P. Chau, Steve C.L. Yuen, Chiu-Sing Choy, Philip H.W. Leong and Kong-Pang Pun, "Architecture and Design Flow for a Highly Efficient Structured ASIC," to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5] Sam M.H. Ho, Steve C.L. Yuen, Hiu Ching Poon, Thomas C.P. Chau, Yan-Qing Ai, Philip H.W. Leong, Oliver C.S. Choy and Kong-Pang Pun, "Structured ASIC:Methodology and Comparison," in Proc. IEEE International Conference on Field-Programmable Technology (FPT), pp. 377-380, 2010.

[6] Thomas C.P. Chau, David W.L. Wu, Yan-Qing Ai, Brian P.W. Chan, Sam M.H. Ho, Oscar K.L. Lau, Kong-Pang Pun, Oliver C.S. Choy, Philip H.W. Leong, "Design of a Single Layer Programmable Structured ASIC Library," in Proc. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 32-35, 2010.

[7] Steve C.L. Yuen, Yan-Qing Ai, Brian P.W. Chan, Thomas C.P. Chau, Sam M.H. Ho, Oscar K.L. Lau, Kong-Pang Pun, Philip H.W. Leong, Oliver C.S. Choy, "Rapid Prototyping on a Structured ASIC Fabric," in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 379 - 380, 2010.

[8] Eddie Hung, Steve Wilton, Thomas C.P. Chau, Haile Yu, and Philip H.W. Leong, "A Detailed Delay Path Model for FPGAs," in Proc. International Conference on Field Programmable Technology (FPT), pp. 96-103, 2009.

[9] Thomas C.P. Chau, Sam M.H. Ho, Philip H.W. Leong, Peter Zipf, and Manfred Glesner, "Generation of Synthetic Floating-point Benchmark Circuits," in Proc. IEEE International Symposium on Parallel and Distributed Processing (IPDPS), pp. 1-9, 2009.

[10] Thomas C.P. Chau, Philip H.W. Leong, Sam M.H. Ho, Brian P.W. Chan, Steve C.L. Yuen, Kong-Pang Pun, Oliver C.S. Choy, and Xinan Wang, "A Comparison of Via-programmable Gate Array Logic Cell Circuits," in Proc. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 53-61, 2009.

Structured ASIC Development

Structured ASIC is an intermediate technology between ASIC and FPGA. It enables the reuse of a single mask set to offer high performance and low non-recurring engineering cost for small to medium volume production. Using structured ASICs allows electronic products to be introduced quickly to market, to have lower cost and to be designed with ease.
The structured ASIC project was directed by three professors from both computer science and electronic engineering departments. It was funded at a level of 5.8 million HKD by the Innovation and Technology Fund of Hong Kong Government and involved collaboration with Hong Kong Applied Science and Technology Research Institute as well as Peking University Shenzhen Graduate School. The main research and development work in the project includes:

  1. Proposing a non-FPGA-like metal programmable fabric for structured ASICs design. An initial study of programmable fabrics is published as one of the 24 paper selected from 92 submission in the 17th ACM International Symposium on Field-Programmable Gate Arrays [1].
  2. Studying methods to quickly map ASICs/FPGAs designs to our structured ASICs, and developing corresponding computer-aided design tools. The results will be published in a paper at the 15th Asia and South Pacific Design Automation Conference [4].
  3. Integrating the structured ASIC with a highly flexible and configurable ASIC to realize an integrated circuit design-and-verification platform that offers short-time to market and low design cost.

Compared to conventional cell-based ASIC technology which uses more than 20 custom layers for a design, our three-custom-layer approach can reduce the total design cost by 90%.

 

Generation of Synthetic Floating-point Benchmark Circuits

Synthetic Floating-Point (SFP) is a synthetic benchmark generator program for floating-point circuits on FPGAs. SFP consists of two independent modules for characterization and generation. The characterization module extracts key dataflow statistics of an arbitrary software program. The generation module involves producing randomized circuits with desired statistics which are either the output of the characterization module or directly generated by the user. Using the basic linear algebra subprograms library, Whetstone benchmark and LINPACK benchmark, it is demonstrated that SFP can be used to generate floating-point benchmarks with different user-specified properties as well as benchmarks that mimic real computational programs. The results are published in [2].

 

A Detailed Delay Path Model for FPGAs

A complete circuit-level description of a representative FPGA is developed, from which a simple delay model as a function of architectural and technology parameters is derived [3]. Using this model, the expression for the optimal delay of any path through the FPGA can be formulated. The model is distilled into being purely architecture dependent, and is used to capture new insight into how FPGA parameters can directly affect its delay. Several applications of this model are:

  1. To gain better intuition of how architecture and process parameters affect the delay path in an FPGA.
  2. For initial studies into new circuit designs and integrated circuit technologies.
  3. In computer-aided design tools for optimization and sensitivity analysis. The technique described can be applied to arbitrary circuits, and experimental results show that our closed form equations give delay values that are accurate to approximately 10% when compared to HSPICE simulations.

 

Hand Gesture Detection System

Chronic use of mouse with improper postures causes mouse-related musculoskeletal injury. A hand gesture detection system (HGDS) is developed as an alternative to control computers. HGDS captures users’ hand positions and figures with a web camera, and correlates the detected information with the system database to determine corresponding actions. Multiple actions are detectable by the system, which users can move the cursor, click, scroll, and use self-define program shortcuts. The Flash tool is used for prototype development, and C++ with OpenCV library is used for final deployment. This project participated in Samsung Joint Universities Creative Technology Talents Awards 2008 and it received an Excellency Award.