LUT-SR uniform random number generators for FPGAs

LUT-SR Uniform Generators for FPGAs

This page has the source code for the paper "FPGA-Optimised Uniform Random Number Generators using LUTs and Shift Registers" which was presented at FPL 2010. The idea of the paper was to design uniform random number generators for FPGAs which provide all of the following properties:

High Quality - The generators pass all common statistical tests for random number quality, and all provide an equidistribution of at least 20 dimensions across all bits.
Long Period - All generators have a period of at least 2¹⁰²⁴-1, and the period scales with the number of bits generated per cycle.
Customisation - The number of bits generated per cycle can be chosen to meet the needs of the application, rather than being tied to artificial 32-bit boundaries inherited from software.
Low resource usage - Each generated bit requires exactly two LUTs and one Flip-Flop.
State serialisation - The state of the RNG can be loaded and retreived at run-time using a built-in three-bit serial interface.
Simple Description - Each RNG can be completely described using a very small algorithm plus a tuple of five small integers (small enough that the C++ algorithm and 60 RNGs all fit in the paper).

This page provides the same LUT-SR generators described in the paper, but as directly usable VHDL which you can (hopefully) just drop into a project.

LUT-SR files:

readme.txt : Current readme for the package.
rng_n1024_r32_t5_k32_s1c48.vhdl : Example of a 32-bit generator provided by the package.
test_rng_n1024_r32_t5_k32_s1c48.vhdl : Test-bench for the 32-bit generator (generated using tools in the package).
lut_sr_v2.zip : Full package, containing the VHDL for multiple generators, and tools for generating test-benches.

Errata

I realised putting source code in a paper was risky, but never mind. Anyway, so far I have found one small bug in the paper, but as it is related to retrieving state from the RNG, and only affects the simulator (not the VHDL), it shouldn't affect anyone. Anwyay, in Listing 1 of the published paper the line:

	int s_out=cs[perm[seedTap]];

	int s_out=cs[cycle[seedTap]];