Units of Memory: Latches
For great animated demonstrations of these concepts, see http://www.play-hookey.com/digital/rs_nand_latch.html
To create a 1-bit memory, we need a logic circuit that "remembers" previous input values (as opposed to the "combinatorial logic" circuits we have seen so far whose output depends only on the current inputs). We can build such a circuit from two NAND gates:
RS NAND Latch
Normally both inputs are held at logic 1. If either is dropped to logic 0, the corresponding output will go to logic 1 and the other will go to logic 0. The outputs will then stay in that state when both inputs return to 1. The circuit has the ability to remember 1 bit or information.
Note that it is forbidden to have both inputs at a logic 0 level at the same time. That state will force both outputs to a logic 1, overriding the feedback latching action. In this condition, whichever input goes to logic 1 first will lose control, while the other input (still at logic 0) controls the resulting state of the latch. If both inputs go to logic 1 simultaneously, the result is a "race" condition, and the final state of the latch cannot be determined ahead of time.
The solution is a slightly more complicated circuit (or other variations of latches/flip-flops):
Clocked D Latch
In the D latch, when the CLK input is logic 1, the Q output will always reflect the logic level present at the D input, no matter how that changes. When the CLK input falls to logic 0, the last state of the D input is trapped and held in the latch, for use by whatever other circuits may need this signal.
Because the single D input is also inverted to provide the signal to reset the latch, this latch circuit cannot experience a "race" condition caused by all inputs being at logic 1 simultaneously. Therefore the D latch circuit can be safely used in any circuit.