Research interests:
- Reconfigurable Computing
- Advanced Computer Architectures
- Parallel Memory Systems
- Hardware/Software Codesign
- Embedded Systems Design
- Fault Tolerant and Dependable Computing
- Systems on Chip
- Computer Systems Testing
General and Program chair:
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29th IEEE International Conference on Computer Design (ICCD'11) (General Chair)
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9th IEEE Symposium on Application Specific Processors (SASP'2011) (General co-Chair)
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28th IEEE International Conference on Computer Design (ICCD'10) (General Chair)
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8th IEEE Symposium on Application Specific Processors (SASP'2010) (Program co-Chair)
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ACM International Conference on Computing Frontiers (CF'09) (Program Co-chair)
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27th IEEE International Conference on Computer Design (ICCD'09) (Program co-Chair)
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26th IEEE International Conference on Computer Design (ICCD'08) (Program Chair)
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SAMOS VII: Embedded Computer Systems: Architectures, MOdeling, and Simulation (General chair)
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XXV IEEE International Conference on Computer Design (ICCD'07) (Processor Architecture Track co-Chair)
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SAMOS VI: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Program chair)
Courses:
I am teaching CO405H-Computing in Space with OpenSPL.
You can use WebIDE for you course project work and more programming in space fun.
Publications:
At dblp and also on Google Scholar.
(some recent awards)
ACM/SIGARCH 24th International Conference on Supercomputing (ICS'10) Tsukuba, Japan, June 2010. Best paper award
Workshop in Information Security Theory and Practices 2007 (WiSTP'07), Heraklion, Greece, May 2007. Best student paper award
USENIX/SAGE Large Installation System Administration conference (LISA 2006), Washington DC, USA, Dec 2006. Best paper award
Projects:
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EXA2PRO, RIA H2020-FETHPC-02-2017, European Union, Contract number 801015, 2018-2021
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SDK4ED, RIA H2020-ICT-05-2017, European Union, Contract number 780572, 2018-2021
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LEGaTO, RIA H2020- ICT-05-2017, European Union, Contract number 780681, 2017-2021
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EuroEXA, RIA H2020-FETHPC-01-2016, European Union, Contract number 754337, 2017-2021
COMPLETED PROJECTS
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EXTRA, RIA H2020-FETHPC-2014, Contract number 671653, 2015-2018
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VINEYARD, RIA H2020-ICT-2015, European Union, Contract number 687628, 2016-2019
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AEGLE, RIA H2020-ICT-2014-1, European Union, Contract number 644906, 2015-2019
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CloudLightning, RIA H2020-ICT-2014-1, European Union, Contract number 643946, 2015-2018
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EUROSERVER, IP FP7-ICT10, Computing Systems, European Union, Contract number 610456, 2013-2016
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ProMSys: Programmable Multicore Systems, The Swedish research council VR, 2011-2014
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EYE: Empowering Young Explorers, CSA FET-ICT-2013-C, EU, Contract number 619241, 2013-2015
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on-Demand System Reliability (DeSyRe), STREP FP7-ICT7, Computing Systems, EU, Contract number 287611, 2011-2014
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Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration (FASTER), STREP FP7-ICT7, Computing Systems, European Union, Contract number 287804, 2011-2014
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ENabling technologies for a programmable many-CORE (ENCORE), STREP FP7-ICT4, Computing Systems, European Uni, Contract number 249059, 2010-2013
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Google Inc. personal research award Configurable Accelerators for Google Applications, Jan 2009-2011
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(Project coordinator of) Scalable Processor Architecture (SARC), Integrated project FP6, European Union, Contract number 27648, 2006-2010
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Smart Cohlear Implants, SmartSIP, STW, 2008-2012
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MISAT, Bsik subsidie, MicroNed, 2005-2009
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High-Performance Architectures and Compilers (HiPEAC-2), Network of excellence of the European Union FP7, Contract number IST-217068, 2008-2012
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High-Performance Architectures and Compilers (HiPEAC), Network of excellence of the EU FP6, Contract number IST-004408, 2003-2007
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VALICHIP, Point-One, 2007-2009
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hARTES, EU FP6 Priority 2.5.3 Embedded Systems, Integrated project, Contract number 035143, 2007-2010
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Reliability techniques for implantable processors, Frame program 3TU with IMEC-NL (Samenwerking HOLST Center), 2007-2010
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Scientific Multicore Vector processors, NUFFIC, (2x PhD students), 2007-2009
My research is/was funded by:
PhD Alumni/ae
- Christos Strydis, Universal Processor Architecture for Biomedical Implants: The SiMS Project, 15 March 2011
External Examiners: Yale Patt, Alex Veidenbaum, Dirk De Ridder
(first job: Post Doc at Erasmus Medical Center, the Netherlands)
- Dimitris Theodoropoulos,Custom Architecture for Immersive-audio Applications (with Georgi Kuzmanov), 9 May 2011
External Examiners: Walid Najjar, Dionissis Pnevmatikatos, Edoardo Charbon
(first job: Post Doc at Technical University of Crete, Greece)
- Thomas Marconi, Efficient Runtime Management of Reconfigurable Hardware Resources, 29 June 2011
External Examiners: Walid Najjar, Jarmo Takala, Dionissis Pnevmatikatos
(first job: Post Doc at the National University of Singapore (NUS), Singapore)
- Daniele Ludovici, Technology Aware Network-on-Chip Connectivity and Synchronization Design (with Davide Bertozzi), 30 June 2011
External Examiners: Luigi Carro, Dionissis Pnevmatikatos, Gerard Smit
(first job: Post Doc at the University of Ferrara, Italy)
- Yi Lu, Realistic Online Resource Management for Partially Reconfigurable Systems, 11 July 2011
External Examiners: Apostolos Dollas, Neil Bergmann, Lars Svensson
(first job: Researcher at ASML, the Netherlands)
- Chunyang Gou, Customizable Memory Schemes for Data Parallel Accelerators, 6 September 2011
External Examiners: Andre Seznec, Per Stenstrom, Jarmo Takala
(first job: PostDoc at TU Delft, the Netherlands)
- Sebastian Isaza, Multicore Architectures for Bioinformatics Applications, 3 October 2011
External Examiners: Nikitas Dimopoulos, Alex Ramirez, Holger Blume
(first job: PostDoc at Erasmus Medical Center, the Netherlands)
- Catalin Ciobanu, Customizable Register Files for Multidimensional SIMD Architectures (with Georgi Kuzmanov), 3 March 2013
External Examiners: Yale Patt, Peter Hofstee, Per Stenstrom
(first job: PostDoc at Chalmers University of Technology, Sweden)
- Rouzbeh Amini, Wireless Communication onboard Spacecraft (co-supervised with Eberhard Gil from Aerospace Engineering), 6 September 2016
External Examiners: Alex Veidenbaum, M.H.G. Verhaegen, D.G. Simons, J. Leijtens
(first job: European Space Agency, the Netherlands)
- Ghazaleh Nazarian, Compiler Assisted Reliability Optimizations, 15 February 2019
External Examiners: Luigi Carro, A. Shahbahrami, J.H.M. Frijns
(first job: BrightSpace, the Netherlands)
PhD students
- Zhijiang Chang
- Bogdan Spinean
- Nils Voss
- Marco Barbone
- Remi Brandt
- Abbas Khan
- Philip Yankov
PhD External Examiner
- M. Mohammadi, An Accelerator for Machine Learning Based Classifiers, Indian Institute of Science, India, November 2017
- S. Mazumdar, Dataflow Thread Management at High-Performance Network-On-Chip Level, University of Siena, Italy, July 2017
- M. Duric, Specialization and Reconfiguration of Lightweight Mobile Processors for Data-Parallel Applications, UPC, Spain, February 2016
- A. Podobas, Improving Performance and Quality-of-Service through the Task-Parallel model, KTH, Sweden, November 2015
- A. Morari, Scalable System Software for High Performance Large-scale Applications, UPC, Spain, June 2014
- P. Burgio, Use of shared memory in the context of embedded multi-core processors: exploration of the technology and its limits, Universite de Bretagne-Sud and University of Bologna, France/Italy, December 2013
- F. Anjam, Dynamically reconfigurable VLIW processors, TU Delft, the Netherlands, August 2013
- S. Lyberis, Manycore platforms and bare metal runtime systems, University of Crete, Greece, July 2013
- P. Jaaskelainen, From Parallel Programs to Customized Parallel Processors, TU Tampere, Finland, December 2012
- N. Sonmez, A multicore emulator with a profiling infrastructure for Transactional Memory on FPGA, UPC, Spain, September 2012
- M. Shafiq, Architectural Explorations for Streaming Accelerators with Customized Memory Layouts, UPC, Spain, May 2012
- N. Harb, Exploring FPGA Dynamic Partial Reconfiguration in Automotive and Multimedia Systems, Universite de Valenciennes, France, Sept 23, 2011
- F. Cabarcas, Castell: a heterogeneous GMP architecture, UPC, Spain, Sept 19, 2011
- R. Gonzalez Garcia, Content Aware Architectures, UPC, Spain, December 4, 2009
- F. Khun Jush, Architectural Enhancement for Message Passing Interconnects, University of Victoria, Canada, September 23, 2008
- M. Thuresson, Compression Techniques for Improved Bandwidth and Static Code Size in Computer Systems, Chalmers University, Sweden, September 19, 2008
MSc Alumni/ae
In the period between 2002-18 I supervised and successfully graduated 61 Master of Science (with thesis) and 22 Bachelor of Science students. Four of my MSc students at TU Delft graduated with summa cum laude.
Talks (keynotes and invited lectures):
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High-level programming of data-centric reconfigurable dataflow systems, International Symposium on
High-Level Parallel Programming and Applications, HLPP 2019, Linkoping University, Linkoping, Sweden, 4 July 2019
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Is Computer Architecture in 2019 Back to the Future?, Yale: 80 in 2019, Universitat Politecnica de Catalunya, Barcelona, Spain, 1 July 2019
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Building Cumulonimbus Cloud Systems (or how to make massive scale computer systems), Smart Systems Summit (SSS 2018), Eindhoven, the Netherlands, 11 October 2018
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Computer Architecture is dead, long live Computer Systems Architecture!, Technical University of Sofia, Bulgaria, 15 May 2018
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Multicores, Manicores, KiloCore? what about no cores at all, Swedish Multicore Days, SICS, Kista, Sweden, 29 November 2017
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Enhancing PRACE with Multiscale Dataflow Capabilities, Julich Supercomputing Centre (JSC), 11 August 2017
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Dataflow Engines in the Cloud, University of Sienna, Italy, 3 July 2017
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Using, Understanding and Programming Data Flow Engines, University of California Riverside, USA, 31 May 2017
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Elastic Dataflow Engines for the Masses, Reconfigurable Architectures Workshop 2017, IPDPS, Orlando, USA, 30 May 2017
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Dataflow for GeoComputing, European Centre for Medium-Range Weather Forecasts, Reading, UK, 11 April 2017
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Computing in Space with Dataflow Engines, Universidad de Antioquia, Medellin, Colombia, 25 January 2017
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Dataflow Supercomputers, Alan Turing Institute Systems Conference, Alan Turing Institute, London, UK, August 3, 2016
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The Future of Reconfigurable Systems: an Industrial Perspective, FRESH 2016, Imperial College, London, UK, July 11, 2016
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Deploying Dataflow Computing in Finance, The 27th Annual IEEE International Conference on
Application-specific Systems, Architectures and Processors (ASAP 2016), London, UK, July 7, 2016
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Programming in Space towards Exascale Computational Densities, Maison de la Simulation, CEA, Paris, France, January 19, 2016
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Computing in Space with OpenSPL, TU/e, Eindhoven, the Netherlands, December 17, 2015
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Computing in Space with OpenSPL, KTH, Stockholm, Sweden, November 9, 2015
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Spatial Computing to Accelerate Science, INESC-ID, Lisbon, Portugal, April 1, 2015
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Everything You Always Wanted to Know About Dataflow Engines Virtualization, MULTIPROG at HiPEAC-15, Amsterdam, the Netherlands, January 20, 2015
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DataFlow Engines in the Clouds: Challenges an Opportunities, Workshop on Reconfigurable Computing (HiPEAC), Amsterdam, the Netherlands, January 20, 2015
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The Spatial Future of Computing, University of Calgary, Calgary, Canada, February 12, 2014
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Computing in Space with OpenSPL, Rice University, Houston, USA, February 11, 2014
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The Spatial Future of Computing (or programming in 2D space now), Texas A&M University, College Station, USA, February 10, 2014
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The Spatial Future of Computing, University of Texas at Austin, Austin, USA, February 6, 2014
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Computing in 2D Space: OpenSPL towards exascale and mobile petascale systems, IBM Research, Austin, USA, February 6, 2014
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OpenSPL: Is Computing in Space the path towards exascale systems, Tampere University of Technology, Tampere, Finland, January 24, 2014
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Affordable 100petaFLOPS systems with Multiscale Dataflow, SCALPERF 13, Bertinoro, Italy, September 23, 2013
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Customizing Memory Accesses to the NoC manycore era, International Workshop on Emerging Topics in NoC-aware Computer Architecture, at the 40th Annual International Symposium on Computer Architecture ISCA, Tel Aviv, Israel, June 23, 2013
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Efficient GPGPU Memory Management for the Masses (E=GM^3), Multicore Architectures and Their Effective Operation 2012, Barcelona, Spain, June 28, 2012
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Sequence Allignment Application Model for Multi-and Manycore Architecturtes, 25th International conference on Information Technologies (InfoTech-2011), Varna, Bulgaria, September 15, 2011
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Alleviating On-chip Shared Memory Bank Conflicts in Data Parallel Accelerators, Electronics 2011, Sozopol, Bulgaria, September 14, 2011
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The SARC Task-centric Architecture and Programming Model, University of Amsterdam (UvA), May 30, 2011
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Is reconfigurable acceleration promising for Google Applications?, Google Inc, Mountain View, USA, February 25, 2010
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HiPEAC addresses the long-term multicore research challenges, HiPEAC 8-th Industrial workshop, Wroclaw, Poland, October 26, 2009
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SARC - the future scalable heterogeneous architecture and its programing model, keynote at the 2-nd Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG), Paphos, Cyprus, January 25, 2009
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Embedded Architectures for Bioinformatics, Workshop Frontiers of High Performance Embedded Computing, Bangalore, India, January 14-16, 2009
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Polymorphic processors and toolchains, Workshop Frontiers of High Performance Embedded Computing, Bangalore, India, January 14-16, 2009
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The MOLEN Polymorphic Processor and its Dedicated Tool Chain, University of Victoria, British Columbia, Canada, September, 2008
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SARC- the status after 2 years, CASTNESS Artist2 NoE workshop, Rome, Italy, January 2008
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SARC, Session on relevant EU projects, HiPEAC 4-th Industrial Workshop, Cambridge, UK, November 2007
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The MOLEN polymorphic processor and its dedicated toolchain, UC Riverside and UC Irvine, October 2007
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SARC: Systematic scalable approach to systems design: From small energy critical embedded systems to large scale networked data servers, Workshop on Directions in FPGAs and Reconfigurable Systems: Design, Programming and Technologies for adaptive heterogeneous Systems-on-Chip and their European Dimensions, DATE Conference 2007, Nice, France, April 2007
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Polymorphic Processors: How to Expose Arbitrary Hardware Functionality to Programmers, Guest lecture, Department of Electronic systems, Aalborg Universiteit, Denmark, April 2007
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SARC overview, Computing Architectures and Software Tools for Numerical Embedded Scalable Systems workshop and school, CASTNESS, Rome, Italy, January 2007
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Reconfigurable processors and programming paradigms, guest lecture, Technical University of Sofia, Bulgaria, May 2005
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Trusted Computing Platform, a quick look under the hood, AEGEE Symposium What they don't tell us; privacy and security on the computer, Utrecht, Netherlands, April 2004
Some Recommended Sites:
Industrial products I helped to become reality:
Prontomail Screen Phone P112: Design & Engineering Showcase Award, CES 1999.
For more examples, see CPS Europe and Pijnenburg HC (now ebmpapst Heating Systems) home pages
Short about me:
Some time ago (1964) I was born in one of the oldest (trust me on this one) cities in Europe.
The modern name of the city is Plovdiv (this is in Bulgaria), however it is also known as:
Kendros, Kendrisas, Eumolpia, Philippopolis, Pulpudeva, Thrimonzium, Pulden, Populdin, Ploudin and Filibe.
This is actually a short list considering the city exists for 6,000 to 8,000 years.
You can read more about Plovdiv
on Wikipedia, on its official .net
web page or on
plovdivguide.com. Being older than most of the oldest towns like Rome, Athens or Constantinople,
an almost contemporary of Troy, Plovdiv is a town built upon layers of towns and bears a culture
developed upon many layers of different cultures. There is also a nice movie about Plovdiv
here and another one with more realistic
colors, screen shots and spoken in English here.
After my studies in Plovidv at the 42-nd elementary school "N.J. Vapcarov" (the same primary school
Hristo Stoitchkov
used to hate very much) and the Secondary school of Electrical Engineering and Electronics "V.I. Lenin" (also
known as TET Lenin), I went to Leningrad for my University study at Voenmech
one of the best Technical Universities in the formal USSR. Needless to say, first I had to spend two years of
my life in the Bulgarian army (having fun with microwave radars) before going to Leningrad (another great city with much
shorter history but many names, called St. Petersburg right now).
On return I spent some very limited time working for Kintex Ltd and much longer working for System Engineering Ltd in Pravetz (R.I.P.) (having fun with IBM PC compatible computers and their peripherals). At the beginning of the 90's I moved to the Netherlands and joined Pijnenburg Microelectronics and Software in Vught to continue having
fun with various Embedded Systems designs now. Pijnenburg (later split into Pijnenburg Heating Controls, CPS and Securalink) was a great company with excellent engineers covering a wide variety of topics and even more exciting projects spanning from cheap smart card readers up to high-end multicore crypto chips (yes we had products with more than two processors on a single chip before 2000). My excellent colleagues and projects are just too many to enlist here. It was just great! During my time at CPS I had the luck to work together with BitWise and the software written by its engineers was truly rock solid. No wonder we remind close friends with several key people in Dunfermline, Eindhoven and also Bill who operates from some strange location in Belgium. Bill's name is Hewlett and he is not related to the HP co-founder. If only HP had Bill in its team, the current marketing and commercial positions would be much stronger.
In March 2002 I started as an Assistant Professor at the Computer Engineering laboratory led by Stamatis Vassiliadis at the faculty of Electrical Engineering, Mathematics and Computer Science, TU Delft, the Netherlands. Unfortunately we (the entire community of computer engineers) lost Stamatis in 2007. Few years later in 2011 after many PhD and MSc students graduations I moved to Sweden to join the Computer Architecture team at Chalmers University of Technology in Sweden where I held the Chair in Computer Systems Engineering. In the fall of 2014 I joined Maxeler Technologies in London for a one year sabbatical and few months later it became apparent that I would not be able to return back to Sweden. It is clear that my "mental age" does not allow me to sit quietly on a "Chair" for the reminder of my carrier (I have no comments about my biological and true ages here). At Maxeler we are very keen on pushing the boundaries of energy efficiency of supercomputers to levels impossible with other technologies. As I used to say on many occasions, only the future knows what is next (excluding taxes and the very final destination according to Edward Ward, Christopher Bullock and possibly Franklin and Twain) so we just have to wait and see.
Last Modified on 18 May 2020 by Georgi Gaydadjiev.