Input Bits: 6
Output Bits: 6
Processing gates: 30
Ordered: TRUE
Gate List: 
Gate 0 (Source X) 
  Output 0 (bit 0)  connected to 1 pin 0

Gate 1 (sqrtNOT1 X) 
  Input 0 (bit 0)  connected to 0 pin 0
  Output 0 (bit 0)  connected to 4 pin 0

Gate 2 (Source X) 
  Output 0 (bit 1)  connected to 3 pin 0

Gate 3 (sqrtNOT2 X) 
  Input 0 (bit 1)  connected to 2 pin 0
  Output 0 (bit 1)  connected to 5 pin 0

Gate 4 (sqrtNOT1 X) 
  Input 0 (bit 0)  connected to 1 pin 0
  Output 0 (bit 0)  connected to 36 pin 0

Gate 5 (sqrtNOT2 X) 
  Input 0 (bit 1)  connected to 3 pin 0
  Output 0 (bit 1)  connected to 36 pin 1

Gate 6 (sqrtNOT3 X) 
  Input 0 (bit 0)  connected to 37 pin 0
  Output 0 (bit 0)  connected to 8 pin 0

Gate 7 (sqrtNOT4 X) 
  Input 0 (bit 1)  connected to 37 pin 1
  Output 0 (bit 1)  connected to 10 pin 0

Gate 8 (sqrtNOT3 X) 
  Input 0 (bit 0)  connected to 6 pin 0
  Output 0 (bit 0)  connected to 9 pin 0

Gate 9 (Sink X) 
  Input 0 (bit 0)  connected to 8 pin 0

Gate 10 (sqrtNOT4 X) 
  Input 0 (bit 1)  connected to 7 pin 0
  Output 0 (bit 1)  connected to 11 pin 0

Gate 11 (Sink X) 
  Input 0 (bit 1)  connected to 10 pin 0

Gate 12 (Source X) 
  Output 0 (bit 2)  connected to 13 pin 0

Gate 13 (sqrtNOT1 X) 
  Input 0 (bit 2)  connected to 12 pin 0
  Output 0 (bit 2)  connected to 16 pin 0

Gate 14 (Source X) 
  Output 0 (bit 3)  connected to 15 pin 0

Gate 15 (sqrtNOT2 X) 
  Input 0 (bit 3)  connected to 14 pin 0
  Output 0 (bit 3)  connected to 17 pin 0

Gate 16 (sqrtNOT1 X) 
  Input 0 (bit 2)  connected to 13 pin 0
  Output 0 (bit 2)  connected to 38 pin 0

Gate 17 (sqrtNOT2 X) 
  Input 0 (bit 3)  connected to 15 pin 0
  Output 0 (bit 3)  connected to 38 pin 1

Gate 18 (sqrtNOT3 X) 
  Input 0 (bit 2)  connected to 39 pin 0
  Output 0 (bit 2)  connected to 20 pin 0

Gate 19 (sqrtNOT4 X) 
  Input 0 (bit 3)  connected to 39 pin 1
  Output 0 (bit 3)  connected to 22 pin 0

Gate 20 (sqrtNOT3 X) 
  Input 0 (bit 2)  connected to 18 pin 0
  Output 0 (bit 2)  connected to 21 pin 0

Gate 21 (Sink X) 
  Input 0 (bit 2)  connected to 20 pin 0

Gate 22 (sqrtNOT4 X) 
  Input 0 (bit 3)  connected to 19 pin 0
  Output 0 (bit 3)  connected to 23 pin 0

Gate 23 (Sink X) 
  Input 0 (bit 3)  connected to 22 pin 0

Gate 24 (Source X) 
  Output 0 (bit 4)  connected to 25 pin 0

Gate 25 (sqrtNOT1 X) 
  Input 0 (bit 4)  connected to 24 pin 0
  Output 0 (bit 4)  connected to 28 pin 0

Gate 26 (Source X) 
  Output 0 (bit 5)  connected to 27 pin 0

Gate 27 (sqrtNOT2 X) 
  Input 0 (bit 5)  connected to 26 pin 0
  Output 0 (bit 5)  connected to 29 pin 0

Gate 28 (sqrtNOT1 X) 
  Input 0 (bit 4)  connected to 25 pin 0
  Output 0 (bit 4)  connected to 30 pin 0

Gate 29 (sqrtNOT2 X) 
  Input 0 (bit 5)  connected to 27 pin 0
  Output 0 (bit 5)  connected to 30 pin 1

Gate 30 (Flip1 Gate) 
  Input 0 (bit 4)  connected to 28 pin 0
  Input 1 (bit 5)  connected to 29 pin 0
  Output 0 (bit 4)  connected to 40 pin 0
  Output 1 (bit 5)  connected to 40 pin 1

Gate 31 (sqrtNOT4 X) 
  Input 0 (bit 5)  connected to 40 pin 1
  Output 0 (bit 5)  connected to 34 pin 0

Gate 32 (sqrtNOT3 X) 
  Input 0 (bit 4)  connected to 40 pin 0
  Output 0 (bit 4)  connected to 33 pin 0

Gate 33 (sqrtNOT3 X) 
  Input 0 (bit 4)  connected to 32 pin 0
  Output 0 (bit 4)  connected to 35 pin 0

Gate 34 (sqrtNOT4 X) 
  Input 0 (bit 5)  connected to 31 pin 0
  Output 0 (bit 5)  connected to 41 pin 0

Gate 35 (Sink X) 
  Input 0 (bit 4)  connected to 33 pin 0

Gate 36 (Flip1 Gate) 
  Input 0 (bit 0)  connected to 4 pin 0
  Input 1 (bit 1)  connected to 5 pin 0
  Output 0 (bit 0)  connected to 37 pin 0
  Output 1 (bit 1)  connected to 37 pin 1

Gate 37 (Flip2 Gate) 
  Input 0 (bit 0)  connected to 36 pin 0
  Input 1 (bit 1)  connected to 36 pin 1
  Output 0 (bit 0)  connected to 6 pin 0
  Output 1 (bit 1)  connected to 7 pin 0

Gate 38 (Flip1 Gate) 
  Input 0 (bit 2)  connected to 16 pin 0
  Input 1 (bit 3)  connected to 17 pin 0
  Output 0 (bit 2)  connected to 39 pin 0
  Output 1 (bit 3)  connected to 39 pin 1

Gate 39 (Flip2 Gate) 
  Input 0 (bit 2)  connected to 38 pin 0
  Input 1 (bit 3)  connected to 38 pin 1
  Output 0 (bit 2)  connected to 18 pin 0
  Output 1 (bit 3)  connected to 19 pin 0

Gate 40 (Flip2 Gate) 
  Input 0 (bit 4)  connected to 30 pin 0
  Input 1 (bit 5)  connected to 30 pin 1
  Output 0 (bit 4)  connected to 32 pin 0
  Output 1 (bit 5)  connected to 31 pin 0

Gate 41 (Sink X) 
  Input 0 (bit 5)  connected to 34 pin 0



pre-simulation amplitudes:
|000001> = 1
Total probability: 1

Adding gate 1 3 4 5 6 7 8 10 13 15 16 17 18 19 20 22 25 27 28 29 30 31 32 33 34 36 37 38 39 40 

After adding all: 
Gates: 1 3 4 5 6 7 8 10 13 15 16 17 18 19 20 22 25 27 28 29 30 31 32 33 34 36 37 38 39 40 , Dependencies 0 2 1 3 37 36 4 5 6 7 12 14 13 15 39 38 16 17 18 19 24 26 25 27 28 29 40 30 32 31 

After sorting all: 
Gates: 34 36 37 38 39 30 40 5 8 10 13 15 18 19 16 17 20 22 25 27 32 31 28 29 33 1 3 6 7 4 , Dependencies 36 37 38 39 30 40 5 12 13 15 18 19 14 16 17 24 25 27 32 31 26 28 29 0 1 3 6 7 2 4 

In partitiion post sort [
Gates: 30 , Dependencies 28 25 24 29 27 26 , 
Gates: 5 , Dependencies 3 2 , 
Gates: 36 , Dependencies 4 1 0 5 3 2 , 
Gates: 38 , Dependencies 16 13 12 17 15 14 , 
Gates: 39 , Dependencies 38 16 13 12 17 15 14 , 
Gates: 40 , Dependencies 30 28 25 24 29 27 26 , 
Gates: 34 , Dependencies 31 40 30 28 25 24 29 27 26 , 
Gates: 37 , Dependencies 36 4 1 0 5 3 2 , 
Gates: 8 , Dependencies 6 37 36 4 1 0 5 3 2 , 
Gates: 10 , Dependencies 7 37 36 4 1 0 5 3 2 , 
Gates: 13 , Dependencies 12 , 
Gates: 15 , Dependencies 14 , 
Gates: 17 , Dependencies 15 14 , 
Gates: 16 , Dependencies 13 12 , 
Gates: 19 , Dependencies 39 38 16 13 12 17 15 14 , 
Gates: 18 , Dependencies 39 38 16 13 12 17 15 14 , 
Gates: 20 , Dependencies 18 39 38 16 13 12 17 15 14 , 
Gates: 22 , Dependencies 19 39 38 16 13 12 17 15 14 , 
Gates: 25 , Dependencies 24 , 
Gates: 27 , Dependencies 26 , 
Gates: 29 , Dependencies 27 26 , 
Gates: 28 , Dependencies 25 24 , 
Gates: 31 , Dependencies 40 30 28 25 24 29 27 26 , 
Gates: 32 , Dependencies 40 30 28 25 24 29 27 26 , 
Gates: 33 , Dependencies 32 40 30 28 25 24 29 27 26 , 
Gates: 1 , Dependencies 0 , 
Gates: 3 , Dependencies 2 , 
Gates: 4 , Dependencies 1 0 , 
Gates: 7 , Dependencies 37 36 4 1 0 5 3 2 , 
Gates: 6 , Dependencies 37 36 4 1 0 5 3 2  ]


Post Partition proc: 

Gates: 30 5 36 38 39 40 34 37 8 10 13 15 17 16 19 18 20 22 25 27 29 28 31 32 33 1 3 4 7 6 , Dependencies 28 25 24 29 27 26 3 2 4 1 0 5 16 13 12 17 15 14 38 30 31 40 36 6 37 7 39 18 19 32 


Post Partition group sort: 

Gates: 30 5 36 38 39 40 34 37 8 10 13 15 17 16 19 18 20 22 25 27 29 28 31 32 33 1 3 4 7 6 , Dependencies 28 25 24 29 27 26 3 2 4 1 0 5 16 13 12 17 15 14 38 30 31 40 36 6 37 7 39 18 19 32 

In partitiion post sort [
Gates: 30 , Dependencies 28 25 24 29 27 26 , 
Gates: 5 , Dependencies 3 2 , 
Gates: 36 , Dependencies 4 1 0 5 3 2 , 
Gates: 17 , Dependencies 15 14 , 
Gates: 16 , Dependencies 13 12 , 
Gates: 40 , Dependencies 30 28 25 24 29 27 26 , 
Gates: 34 , Dependencies 31 40 30 28 25 24 29 27 26 , 
Gates: 37 , Dependencies 36 4 1 0 5 3 2 , 
Gates: 8 , Dependencies 6 37 36 4 1 0 5 3 2 , 
Gates: 10 , Dependencies 7 37 36 4 1 0 5 3 2 , 
Gates: 13 , Dependencies 12 , 
Gates: 15 , Dependencies 14 , 
Gates: 38 , Dependencies 16 13 12 17 15 14 , 
Gates: 39 , Dependencies 38 16 13 12 17 15 14 , 
Gates: 19 , Dependencies 39 38 16 13 12 17 15 14 , 
Gates: 18 , Dependencies 39 38 16 13 12 17 15 14 , 
Gates: 20 , Dependencies 18 39 38 16 13 12 17 15 14 , 
Gates: 22 , Dependencies 19 39 38 16 13 12 17 15 14 , 
Gates: 25 , Dependencies 24 , 
Gates: 27 , Dependencies 26 , 
Gates: 29 , Dependencies 27 26 , 
Gates: 28 , Dependencies 25 24 , 
Gates: 31 , Dependencies 40 30 28 25 24 29 27 26 , 
Gates: 32 , Dependencies 40 30 28 25 24 29 27 26 , 
Gates: 33 , Dependencies 32 40 30 28 25 24 29 27 26 , 
Gates: 1 , Dependencies 0 , 
Gates: 3 , Dependencies 2 , 
Gates: 4 , Dependencies 1 0 , 
Gates: 7 , Dependencies 37 36 4 1 0 5 3 2 , 
Gates: 6 , Dependencies 37 36 4 1 0 5 3 2  ]


Subgroup proc: 
Gate 30 (Flip1 Gate) 
  Input 0 (bit 4)  connected to 28 pin 0
  Input 1 (bit 5)  connected to 29 pin 0
  Output 0 (bit 4)  connected to 40 pin 0
  Output 1 (bit 5)  connected to 40 pin 1

Gate 5 (sqrtNOT2 X) 
  Input 0 (bit 1)  connected to 3 pin 0
  Output 0 (bit 1)  connected to 36 pin 1

Gate 36 (Flip1 Gate) 
  Input 0 (bit 0)  connected to 4 pin 0
  Input 1 (bit 1)  connected to 5 pin 0
  Output 0 (bit 0)  connected to 37 pin 0
  Output 1 (bit 1)  connected to 37 pin 1

Gate 17 (sqrtNOT2 X) 
  Input 0 (bit 3)  connected to 15 pin 0
  Output 0 (bit 3)  connected to 38 pin 1

Gate 16 (sqrtNOT1 X) 
  Input 0 (bit 2)  connected to 13 pin 0
  Output 0 (bit 2)  connected to 38 pin 0

Gate 40 (Flip2 Gate) 
  Input 0 (bit 4)  connected to 30 pin 0
  Input 1 (bit 5)  connected to 30 pin 1
  Output 0 (bit 4)  connected to 32 pin 0
  Output 1 (bit 5)  connected to 31 pin 0

Gate 34 (sqrtNOT4 X) 
  Input 0 (bit 5)  connected to 31 pin 0
  Output 0 (bit 5)  connected to 41 pin 0

Gate 37 (Flip2 Gate) 
  Input 0 (bit 0)  connected to 36 pin 0
  Input 1 (bit 1)  connected to 36 pin 1
  Output 0 (bit 0)  connected to 6 pin 0
  Output 1 (bit 1)  connected to 7 pin 0

Gate 8 (sqrtNOT3 X) 
  Input 0 (bit 0)  connected to 6 pin 0
  Output 0 (bit 0)  connected to 9 pin 0

Gate 10 (sqrtNOT4 X) 
  Input 0 (bit 1)  connected to 7 pin 0
  Output 0 (bit 1)  connected to 11 pin 0

Gate 13 (sqrtNOT1 X) 
  Input 0 (bit 2)  connected to 12 pin 0
  Output 0 (bit 2)  connected to 16 pin 0

Gate 15 (sqrtNOT2 X) 
  Input 0 (bit 3)  connected to 14 pin 0
  Output 0 (bit 3)  connected to 17 pin 0

Gate 38 (Flip1 Gate) 
  Input 0 (bit 2)  connected to 16 pin 0
  Input 1 (bit 3)  connected to 17 pin 0
  Output 0 (bit 2)  connected to 39 pin 0
  Output 1 (bit 3)  connected to 39 pin 1

Gate 39 (Flip2 Gate) 
  Input 0 (bit 2)  connected to 38 pin 0
  Input 1 (bit 3)  connected to 38 pin 1
  Output 0 (bit 2)  connected to 18 pin 0
  Output 1 (bit 3)  connected to 19 pin 0

Gate 19 (sqrtNOT4 X) 
  Input 0 (bit 3)  connected to 39 pin 1
  Output 0 (bit 3)  connected to 22 pin 0

Gate 18 (sqrtNOT3 X) 
  Input 0 (bit 2)  connected to 39 pin 0
  Output 0 (bit 2)  connected to 20 pin 0

Gate 20 (sqrtNOT3 X) 
  Input 0 (bit 2)  connected to 18 pin 0
  Output 0 (bit 2)  connected to 21 pin 0

Gate 22 (sqrtNOT4 X) 
  Input 0 (bit 3)  connected to 19 pin 0
  Output 0 (bit 3)  connected to 23 pin 0

Gate 25 (sqrtNOT1 X) 
  Input 0 (bit 4)  connected to 24 pin 0
  Output 0 (bit 4)  connected to 28 pin 0

Gate 27 (sqrtNOT2 X) 
  Input 0 (bit 5)  connected to 26 pin 0
  Output 0 (bit 5)  connected to 29 pin 0

Gate 29 (sqrtNOT2 X) 
  Input 0 (bit 5)  connected to 27 pin 0
  Output 0 (bit 5)  connected to 30 pin 1

Gate 28 (sqrtNOT1 X) 
  Input 0 (bit 4)  connected to 25 pin 0
  Output 0 (bit 4)  connected to 30 pin 0

Gate 31 (sqrtNOT4 X) 
  Input 0 (bit 5)  connected to 40 pin 1
  Output 0 (bit 5)  connected to 34 pin 0

Gate 32 (sqrtNOT3 X) 
  Input 0 (bit 4)  connected to 40 pin 0
  Output 0 (bit 4)  connected to 33 pin 0

Gate 33 (sqrtNOT3 X) 
  Input 0 (bit 4)  connected to 32 pin 0
  Output 0 (bit 4)  connected to 35 pin 0

Gate 1 (sqrtNOT1 X) 
  Input 0 (bit 0)  connected to 0 pin 0
  Output 0 (bit 0)  connected to 4 pin 0

Gate 3 (sqrtNOT2 X) 
  Input 0 (bit 1)  connected to 2 pin 0
  Output 0 (bit 1)  connected to 5 pin 0

Gate 4 (sqrtNOT1 X) 
  Input 0 (bit 0)  connected to 1 pin 0
  Output 0 (bit 0)  connected to 36 pin 0

Gate 7 (sqrtNOT4 X) 
  Input 0 (bit 1)  connected to 37 pin 1
  Output 0 (bit 1)  connected to 10 pin 0

Gate 6 (sqrtNOT3 X) 
  Input 0 (bit 0)  connected to 37 pin 0
  Output 0 (bit 0)  connected to 8 pin 0

post-simulation amplitudes:
|000100> = -0.5
|000101> = 0.5
|000110> = -0.5
|000111> = -0.5
Total probability: 1


Completed in 0.331 seconds.