Dynamically Calibrating Clock Rate for FPGAs
J. Bower, O. Mencer, W. Luk, M. J. Flynn, M. Morf
[CoolChips, Yokohama, April 2005]

abstract.

Field-Programmable Gate Arrays (FPGAs) provide a substrate for dynamic circuit
optimization and adaption. For example, by customizing the datapath and running
at the minimal clock frequency, it is possible for an FPGA to be up to ten
times better--in terms of performance/power--compared to a low power embedded
microprocessor. More recently, there is also increased interest in hotspot
management of reconfigurable devices.

As we customize FPGA clock frequency--possibly across multiple clock domains--
we can adapt the FPGAs performance and power consumption dynamically to
environmental conditions and computational requirements. Traditionally,
FPGA-vendor specific timing analysis tools statically calculate conservative
estimates for clock frequencies of custom circuits using worst-case models.

In this presentation, we show a methodology for customizing clock frequency
to environmental conditions by including dynamic monitoring and error checking
circuitry into the designs. We back-up our methodology with a number of
experiments using Xilinx Virtex FPGAs and an experimental setup with multiple
clock domains and a set of applications. We show the advantages of dynamically
adjusting clock frequency at multiple temperature points and for a selection
of circuits such as multiplication, DCT (from image processing), and DES
encryption.

Our experiments show performance improvements of over 30% compared to the
conservative estimates of the Xilinx timing analysis tools. In addition,
we show the behavior of bit-errors with agressive clock frequencies. As
expected, the behavior of bit-errors in time and space depends on the
computations of the circuit, and the distribution of the errors can be taken
into account when monitoring the correctness of the underlying computations.