ASC, A Stream Compiler for Computing with FPGAs
[IEEE Transactions on CAD, 2006]

Oskar Mencer

abstract.

ASC, A Stream Compiler for computing with Field Programmable
Gate Arrays (FPGAs) emerges from our ambition to bridge the
hardware design productivity gap where the number of available
transistors grows more rapidly than the productivity of VLSI and
FPGA CAD tools. ASC attacks this problem with a software-like
programming interface to hardware design (FPGAs) while at the same
time keeping the performance of hand-designed circuits. ASC
improves productivity by letting the programmer optimize the
implementation on the algorithm-level, the architecture-level,
the arithmetic-level and the gate-level, all within the same C++
program.

We apply ASC's increased productivity to hardware acceleration
of a wide range of applications. Traditionally hardware accelerators
are tediously hand-crafted to achieve top performance. ASC simplifies
design space exploration of hardware accelerators by transforming the
hardware design task into a software design process, using only 'gcc'
and 'make' to obtain a hardware netlist. Our experience suggests that
hardware design productivity and ease-of-use are close to pure software
development. We present results and case studies with optimizations (a)
on the gate-level: Kasumi and IDEA encryption, (b) on the arithmetic
level: redundant addition and multiplication, function evaluation for
2D rotation, and (c) on the architecture level: Wavelet and LZ-like
compression.