In Priority Order

A) Arithmetic:
1. HWfloat: optimize floating point lib (look at Florent's FP lib)
   http://perso.ens-lyon.fr/jeremie.detrey/FPLibrary/
2. new HWfloat with encoded floating point (i.e. exponent is encoded)
3. HWfix: enable the fixed point to be outside the number
4. saturated arithmetic and overflow management
5. function evalution library and HWlog for HWfix and HWfloat
6. bitwidth minimization for average and max error (via automatic differentiation and ILP formulation)
7. arithmetic: optimize multipliers/dividers/array sqrt, const mult
8. Digit Serial Arithmetic MSB first, LSB first, etc...

B) Applications (focus on floating point):
1. medical image processing (Daniel, Jun?)
2. Financial Computing
3. Scientific Computing (matrix lib: blas 1,2,3, pde solvers, SPECFP)
4. re-implement CC designs: shape-adaptive TM, radiosity/OpenGL, elliptic curve encryption 
5. accelerate JavaVM/.Net
6. circuit enumeration/bitwidth enumeration with ASC
7. Accelerate Spice simulations
8. Accelerate FPGA place and route with ST tools or Toronto tools
9. SPEC benchmarks

C) Gate Level/ASC extensions:
1. build backends for other FPGA cards:
  + RC1000 (PCI): www.doc.ic.ac.uk/~wl/icprojects/adc-rc1000.html
    XCV1000E and XCV2000E; simple interface, VHDL code available,
    can build a cable to link 2 boards together to test
    multi-chip/multi-board designs
  + RC2000 (PCI): large XC2V6000
  + RC200 (standalone with colour LCD): XC2V1000, with ethernet
    interface so potentially can link 2 togther via network
    could try these first; also see if Nallatech would lend us boards?

2. domain-specific/architecture-specific generators
  i.e. systolic arrays, cellular automata (see also higher level loop trafos)
  + graph operations: continue HAGAR work: e.g. hardware graph accelerators for graph coloring, travelling salesman, ....
  + BSAT: mapping apps to BSAT and accelerating that way...
3. testing of ASC features
4. EDIF2EDIF translation: targetting multiple FPGAs, i.e. Altera, EDIF optimization, etc...
5. use CoreGen+Xilinx lib more extensively...through PamDC import interface and maybe even through Pebble.
6. programming multi-FPGA boards and multi-board systems, i.e. linux cluster with FPGA cards on the nodes

D) C++ to ASC:
1. Continue Per's work on bottleneck classification/performance counters, etc...
2. use ROSE/SUIF/TGL for code (loop) transformations
3. automatic memory hierarchy design (i.e. automate decision which variable goes into which memory on/off FPGA
4. RTR extensions to ASC

E) longer term: FUSC: Framework for Unifying SoC Compilers
+ already started interfacing Pebble and Cobble (our Handel-C)
+ final-year project on Quartz, integrating Ruby and Pebble
+ future: involving the above + ASC + Henry's + Gabriel's work
-> split into 2 tasks: combining functionality and combining syntax
=> do for FPGAs/SoC what Microsoft .Net does for software..maybe even reuse ideas and implementations...maybe .Net has an interface for extension through
new languages ... ? 
=> need superior intermediate format....