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- Sixteen very sophisticated processors
- Connected by full crossbar to 64 interleaved memory banks
- Each processor has three floating point arithmetic units, each divided into five
pipeline stages.
- Under ideal circumstances, all three FPUs are fully busy and can complete a FLOP
every cycle
- With a clock rate of 2GHz (cycle time 0.5ns), each processor can achieve 6 GFLOPs
- 16 processors working flat out at 6 GFLOPs each would achieve 96 GFLOPs
- We assume that the memory system can accommodate this
Paul H J Kelly
Mon Nov 17 01:24:12 GMT 1997