...

(costs of pipelining, continued, 1...)

• The memory system must now handle much more traffic (H&P pp.142):
  • BEFORE:

    one instruction fetch (in IF) + one read or write (in MEM) per 5 cycles

  • AFTER: one instruction fetch + one read of write per cycle
• Note that even in the sequential case, we assumed that the memory access latency was one cycle - so using the memory every cycle just uses spare capacity.
• A common way to deal with this is to introduce a separate memory for instructions.
• In practice, instead of two memory systems. We just have two caches, I-cache and D-cache.