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The experiments were performed on a
SPARC 10 model 41 processor with 64 MB RAM:
- This machine has a 40MHz ``SuperSPARC'' pipelined RISC CPU.
- 3-way superscalar
- Separate floating point units for add/subtract and multiply/divide.
- FP add: one cycle latency, FP multiply: three cycles latency
(both fully pipelined).
The compiler used was the GNU C compiler
gcc, version 2.5.7.
Paul H J Kelly
Thu Dec 4 18:15:31 GMT 1997