| BEQZ R10,Label | IF | IS | ||||||||||||
LD |
IF | IS | MEM |
|
WB | |||||||||
| ADDD |
IF | IS | RO | RO | EX | WB | ||||||||
| LD |
IF | IS | MEM |
|
WB | |||||||||
| SUBD F3, |
IF | IS | RO | RO | RO | RO | EX | WB | ||||||
| ADD R4, |
IF | IS | RO | RO | WB | |||||||||
| Issue no. | 1 | 2
Suppose branch is last item of prev issue
(eg ... we block issue of rest of package)
Issue 2 mustn't proceed speculatively
Because it will update several registers
These registers are used to pass values from
inst |
LD
,100(R1)
& & IF & IS & MEM&
& WB
ADDD
,
,F1
& & IF & IS & RO & RO & EX &
& WB
LD
,100(R1)
& & IF & IS & MEM&
& WB
SUBD F3,
,F4
& & IF & IS & RO & RO & RO & RO &
& EX & WB
ADD R4,
,R3
& & IF & IS & RO & RO &
& WB
Issue no.
& 1 & 2
Suppose branch is last item of prev issue
(eg ... we block issue of rest of package)
Issue 2 mustn't proceed speculatively
Because it will update several registers
These registers are used to pass values from
inst
to inst
They would have to be reinstated if the
branch were mispredicted
| BEQZ R10,Label | IF | IS | ||||||||||||
LD |
IF | IS | MEM |
|
WB | |||||||||
| ADDD |
IF | IS | RO | RO | EX | WB | ||||||||
| LD |
IF | IS | MEM |
|
WB | |||||||||
| SUBD F3, |
IF | IS | RO | RO | RO | RO | EX | WB | ||||||
| ADD R4, |
IF | IS | RO | RO | WB | |||||||||
| Issue no. | 1 | 2
Suppose branch is last item of prev issue
(eg ... we block issue of rest of package)
Issue 2 mustn't proceed speculatively
Because it will update several registers
These registers are used to pass values from
inst |
LD
,100(R1)
& & IF & IS & MEM&
& WB
ADDD
,
,F1
& & IF & IS & RO & RO & EX &
& WB
LD
,100(R1)
& & IF & IS & MEM&
& WB
SUBD F3,
,F4
& & IF & IS & RO & RO & RO & RO &
& EX & WB
ADD R4,
,R3
& & IF & IS & RO & RO &
& WB
Issue no.
& 1 & 2
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