Chapter 7 - Parallel architectures, shared memory and cache coherency

Advanced Computer Architecture Chapter 7.14

Multiple caches… and trouble

Suppose processor 0 loads memory location x

x is fetched from main memory and allocated into processor 0’s cache(s)

First-level cache

CPU

second-level cache

First-level cache

CPU

second-level cache

First-level cache

CPU

second-level cache

Interconnection network

Main memory

Processor 0

Processor 1

Processor 2