Chapter 7 - Parallel architectures, shared memory and cache coherency

Advanced Computer Architecture Chapter 7.16

Multiple caches… and trouble

Suppose processor 0 stores to memory location x

Processor 0’s cached copy of x is updated

Processor 1 continues to used the old value of x

First-level cache

CPU

second-level cache

First-level cache

CPU

second-level cache

First-level cache

CPU

second-level cache

Interconnection network

Main memory

Processor 0

Processor 1

Processor 2