Advanced Computer Architecture Chapter 7.26
The job of the cache controller - snooping
The protocol state
transitions are implemented by the cache controller –
which “snoops” all the bus traffic
Transitions are
triggered either by
the bus (Bus
invalidate, Bus write miss, Bus read miss)
The CPU (Read hit,
Read miss, Write hit, Write miss)
For every bus
transaction, it looks up the directory (cache line
state) information for the specified address
If this processor
holds the only valid data (DIRTY), it responds to a “Bus read miss”
by providing the data to the requesting CPU
If the memory copy is
out of date, one of the CPUs will have the cache line in the
SHARED-DIRTY state (because it updated it last) – so must provide data to
requesting CPU
State transition
diagram doesn’t show what happens when a cache line is displaced…