Advanced Computer Architecture Chapter 7.67
Clustered architectures
Idea: systems linked by network
connected via I/O bus
Eg Fujitsu AP3000, Myrinet, Quadrics
Idea: CPU/memory packages linked
by network connecting main memory units
Eg SGI Origin
Idea: CPUs share main memory
Eg Intel Xeon SMP (and many others)
Idea: CPUs share L2/L3 cache
Eg IBM Power4
Idea: CPUs share L1 cache
Idea: CPUs share registers, functional units
Alpha 21464/EV8, Cray/Tera MTA (multithreaded
architecture)•Cunning Idea: do (almost) all the above
at the same time
•Eg IBM
SP/Power4: 2
CPUs/chip sharing L2, multichip module packages/links 4 chips/node, with L3 and
DRAM for each CPU on same
board, with high-speed (ccNUMA) link to other nodes (see