Chapter 7 - Parallel architectures, shared memory and cache coherency

Advanced Computer Architecture Chapter 7.68

Which cache should the cache controller control?

L1 cache is already very busy with CPU traffic

L2 cache also very busy…

L3 cache doesn’t always have the current value for a cache line

1.Although L1 cache is normally write-through, L2 is normally write-back

2.Some data may bypass L3 (and perhaps L2) cache (eg when stream-prefetched)

–In Power4, cache controller manages L2 cache – all external invalidations/requests

–L3 cache improves access to DRAM for accesses both from CPU and from network