Advanced Computer Architecture Chapter 7.30
Implementation
Complications
Write Races:
Cannot update cache
until bus is obtained
Otherwise, another
processor may get bus first, and then write the same cache block!
Two step process:
Arbitrate for bus
Place miss on bus and
complete operation
If miss occurs to
block while waiting for bus, handle miss (invalidate may be needed) and then restart.
Split transaction
bus:
Bus transaction is not
atomic: can have multiple outstanding transactions for a block
Multiple misses can
interleave, allowing two caches to grab block in the Exclusive state
Must track and prevent
multiple misses for one block
Must support
interventions and invalidations