Advanced Computer Architecture Chapter 7.31
Implementing Snooping
Caches
Multiple processors
must be on bus, access to both addresses and data
Add a few new commands
to perform coherency, in addition to read and write
Processors
continuously snoop on address bus
If address matches
tag, either invalidate or update
Since every bus
transaction checks cache tags, could interfere with CPU just to check:
solution 1: duplicate set of tags for
L1 caches just to allow checks in parallel with CPU
solution 2: L2
cache already duplicate, provided L2 obeys inclusion with L1 cache
block size,
associativity of L2 affects L1