Chapter 7 - Parallel architectures, shared memory and cache coherency

Advanced Computer Architecture Chapter 7.36

Directory Protocol

Similar to Snoopy Protocol: Three states

Shared: ≥ 1 processors have data, memory up-to-date

Uncached (no processor hasit; not valid in any cache)

Exclusive: 1 processor (owner) has data;
memory out-of-date

In addition to cache state, must track which processors have data when in the shared state (usually bit vector, 1 if processor has copy)

Keep it simple(r):

Writes to non-exclusive data
=> write miss

Processor blocks until access completes

Assume messages received
and acted upon in order sent