Chapter 7 - Parallel architectures, shared memory and cache coherency

Advanced Computer Architecture Chapter 7.37

Directory Protocol

No bus and don’t want to broadcast:

interconnect no longer single arbitration point

all messages have explicit responses

Terms: typically 3 processors involved

Local node where a request originates

Home node where the memory location
of an address resides

Remote node has a copy of a cache
block, whether exclusive or shared

Example messages on next slide:
P = processor number, A = address