Advanced Computer Architecture Chapter 7.40
CPU -Cache State Machine
State machine
for CPU  requests
for each
memory block
Invalid state
if in
memory
Fetch/Invalidate
send Data Write Back message
to home directory
Invalidate
Invalid
Shared
(read/only)
Exclusive
(read/writ)
CPU Read
CPU Read hit
Send Read Miss
message
CPU Write:
Send Write Miss
msg to h.d.
CPU Write:Send
Write Miss message
to home directory
CPU read hit
CPU write hit
Fetch: send Data Write Back message to home directory
CPU read miss:
Send Read Miss
CPU write miss:
send Data Write Back message
and Write Miss to home
directory
CPU read miss: send Data Write Back message and read miss to home directory