Advanced Computer Architecture Chapter 7.56
Another MP Issue:
Memory Consistency Models
Memory Consistency Models
What is consistency? When must a processor see the new value?
e.g., seems that P1: A =
0; P2: B = 0;
..... .....
A = 1; B = 1;
L1: if (B == 0) ...
L2: if (A == 0)
...
Impossible for both if statements L1 & L2 to be true?
What if write invalidate is delayed & processor continues?
Memory consistency models: what are the rules for such cases?
Sequential consistency: result of
any execution is the same as if the accesses of each
processor were kept in order and the accesses
among different processors were interleaved =>
assignments before ifs aboveSC: delay all memory accesses until all invalidates done