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Four cache
line states:
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Broadcast
invalidations on bus
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unless cache
line is exclusively
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“owned” (DIRTY)
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Read miss:
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If another cache
has the line
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in SHARED-DIRTY
or
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DIRTY,
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it is supplied
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changing state
to SHARED-
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DIRTY
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Otherwise
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the line comes
from memory.
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The state of the
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line is set to
VALID
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Advanced Computer Architecture Chapter 7.24
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