| CPU Read hit |
|
|
|
|
|
| Remote
Write or |
||||
| Miss due to |
||||
| address
conflict |
||||
|
|
|
| Shared |
||
| (read/only) |
||
| Invalid |
| CPU Read |
|
|
| Place read miss |
|
| on bus |
|
|
|
|
|
|
| Remote |
||||
| Write |
||||
| or Miss due to |
||||
| address
conflict |
||||
| Write
back block |
||||
|
|
|
|
| Remote |
|||
| Read |
|||
| Place
Data |
|||
| on
Bus? |
|||
|
|
|
| Remote Read |
||
| Write back |
||
| block |
||
|
|
|
| Place
Write |
||
| Miss
on |
||
| Bus |
||
|
|
|
| Exclusive |
||
| (read/only) |
||
|
|
|
| Modified |
||
| (read/write) |
||
|
|
| CPU read hit |
|
| CPU write hit |
|
|
|
|
| CPU Write |
||
| Place
Write |
||
| Miss
on Bus? |
||
| CPU Read hit |
| Advanced Computer Architecture Chapter 7.28 |