Operating Systems Concepts             Assessed exercise 2

 

Issued:            Monday 9 December 2002

Due:               Monday 13 January 2003, 5pm

 

This exercise sheet is available on-line at http://www.doc.ic.ac.uk/~wjk/OperatingSystemsConcepts

 

Answer all of the following questions:

 

1.      Describe 2 general circumstances under which operating system kernel code is executed.

2.      The following is an unordered list of the steps needed to service an interrupt that occurs during the execution of a user process in the Simple Kernel. Place the steps into the correct (time) order and indicate what entity (i.e. interrupting device, CPU hardware, first-level interrupt handler, second-level interrupt handler or third-level interrupt handler) is responsible for performing each step.

a.   Call third-level interrupt handler for given interrupt number
b.   Enable interrupts (with EXITKERNEL macro)
c.   Set PC from interrupt vector
d.   Execute IRET instruction
e.   Signal interrupt and place interrupt number onto CPU pins
f.    Call second-level interrupt handler, passing interrupt number
g.   Push flag register and PC of user process onto stack
h.   Disable interrupts (with ENTERKERNEL macro)
i.    Pop general registers (of user process) off stack
j.    Pop user process flags and PC off stack
k.   Push general registers (of user process) onto stack
l.    Manipulate kernel data structures (if necessary)
m.  Set flags register from interrupt vector

3.      A paged virtual memory system with 16KB pages is set up on a computer with 32-bit (virtual) address registers, 64MB of physical memory and a (sector-addressable) hard disk with 16KB sectors and a 128MB swap partition. If there are 5 active processes running on the machine,

(a)    How big could the virtual address space of each process be?

(b)   How many page tables would be needed and how many entries should there be in each?

(c)    How big should each entry in the page table be (in bits)?

(d)   If an associative TLB (translation lookaside buffer) with 32 entries (PARs) was introduced to speed up address translation, what would be the size of each entry in the TLB (in bits)? You may assume that PARs are stored along with other registers as part of the context of each process.