Programme for FPL97 Monday, 1st September 1997 0815-0900 Registration (outside Lecture Room 342 in Mechanical Engineering Building) 0900-0915 Welcome Session 1: Devices and Architectures 0915-0940 J. Faura, J.M. Moreno, C. Horton, P.V. Duong, M.A. Aguirre and J.M. Insenser Multicontext dynamic reconfiguration and real time probing on a novel mixed signal programmable device with on-chip microprocessor 0940-1005 T. Miyazaki, A. Takahara, M. Katayama, T. Murooka, T. Ichimori, K. Fukami, A. Tsutsui and K. Hayashi CAD-oriented FPGA and dedicated CAD system for telecommunications 1005-1030 M. Leeser, W.M. Meleis, M.M. Vai and P. Zavracky Rothko: a three dimensional FPGA architecture, its fabrication, and design tools 1030-1130 Break and Poster Session A (parallel with Commercial Presentation I) G. McGregor and P. Lysaght Extending dynamic circuit switching to meet the challenges of new FPGA architectures D. Robinson, P. Lysaght, G. McGregor and H. Dick Performance evaluation of a full speed PCI initiator subsystem using FPGAs T. Do, H. Kropp, M. Schwiegershausen and P. Pirsch Implementation of pipelined multipliers on Xilinx FPGAs S. Nisbet and S.A. Guccione The XC6200DS development system 1100-1115 Commercial Presentation I: Annapolis Micro Systems Session 2: Devices and Systems 1130-1155 E. Boemo and S. Lopez-Buedo Thermal monitoring on FPGAs using ring-oscillators 1155-1220 I. Kostarnov, S. Morley, J. Osmany and C. Solomon A reconfigurable approach to low cost media processing 1220-1245 P.I. Mackinlay, P.Y.K. Cheung, W. Luk and R. Sandiford Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research 1245-1400 Lunch Session 3: Reconfiguration I 1400-1425 B. Kahne and P. Athanas Stream synthesis for a wormhole run-time reconfigurable platform 1425-1450 W. Luk, N. Shirazi, S.R. Guo and P.Y.K. Cheung Pipeline morphing and virtual pipelines 1450-1515 B. Rising, M. van Daalen, P. Burge and J. Shawe-Taylor Parallel Graph colouring using FPGAs 1515-1615 Break and Poster Session B (parallel with Commercial Presentation II) O. Diessel and H. ElGindy Run-time compaction of FPGA designs J.M. Emmert and D. Bhatia Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement J. Leonard and W.H. Mangione-Smith A case study of partially evaluated hardware circuits: key-specific DES R. Payne Run-time parameterised circuits for the Xilinx XC6200 1545-1600 Commercial Presentation II: Xilinx Session 4: Reconfiguration II 1615-1640 G. Brebner Automatic identification of swappable logic units in XC6200 circuitry 1640-1705 P. Lysaght Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic 1705-1730 B.L. Hutchings Exploiting reconfigurability through domain-specific systems 1830-2130 Exhibition and Dinner Tuesday, 2nd September 1997 Session 5: Physical Design Tools 0900-0925 M. Servit and K. Yi Technology mapping by binate covering 0925-0950 V. Betz and J. Rose VPR: A new packing, placement and routing tool for FPGA research 0950-1015 M. Inuani and J. Saul Technology mapping of heterogeneous LUT-based FPGAs 1015-1115 Break and Poster Session C (parallel with Commercial Presentation III) K. Feske, S. Mulka, M. Koegst and G. Elst Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs X. Lin, E. Dagless and A. Lu Technology mapping of LUT based FPGAs for delay optimisation S. Acock and K. Dimond Automatic mapping of algorithms on to multiple FPGA-SRAM modules B. Maunder, Z. Salcic and G. Coghill FPLD HDL synthesis employing high-level evolutionary algorithm optimisation A.V. Chichkov and C.B. Almeida A hardware/software partitioning algorithm for custom computing machines 1045-1100 Commercial Presentation III: TSI TelSys Session 6: Custom Computing and Codesign 1115-1140 E. Lechner and S.A. Guccione The Java environment for reconfigurable computing 1140-1205 R.W. Hartenstein, J. Becker, M. Herz and U. Nageldinger Data scheduling to increase performance of parallel accelerators 1205-1230 R. Kress, R.W. Hartenstein, U. Nageldinger An operating system for custom computing machines based on the Xputer paradigm 1230-1400 Lunch Session 7: Signal Processing 1400-1425 A. Dandalis and V.K. Prasanna Fast parallel implementation of DFT using configurable devices 1425-1450 D. Greenfield, C. Crome, M.S. Won and D. Amos Enhancing fixed point DSP processor performance by adding CPLDs as coprocessing elements 1450-1515 M. Shand A case study of algorithm implementation in reconfigurable hardware and software 1515-1615 Break and Poster Session D (parallel with Commercial Presentation IV) A.S. Chaudhuri, P.Y.K. Cheung and W. Luk A reconfigurable data-localised parallel array architecture for morphological algorithms D. Chauham, M.K. Ibrahim, B. Bramer, A Aggoun Virtual radix array processors T. Mathews, S.G. Gibb, L.E. Turner, P.J.W. Graumann and M. Fattouche FPGA implementation of a matched filter detector for spread spectrum communications systems S. Teerapanyawatt and K. Athikulwongse An NTSC and PAL closed caption processor 1545-1600 Commercial Presentation IV: Embedded Solutions Limited Session 8: Image and Video Processing 1615-1640 T. Kean and A. Duncan A 800 Mpixel/sec reconfigurable image correlator on XC6216 1640-1705 F. Lisa-Mingo, F. Cuadrado, D. Rexachs and J. Carrabina A reconfigurable PCI-based computer vision system 1705-1730 P.A. Dunn and P.I. Corke Real-time stereopsis using FPGAs 1730-1740 A. Keevallik Introduction to FPL98 1900 Banquet Wednesday, 3rd September 1997 Session 9: Communications, Sensors and Graphics 0835-0900 C. Jong, Y. Lam and C. Ng FPGA implementation of a digital IQ demodulator 0900-0925 I. Page Hardware compilation, configurable platforms and ASICs for self-validating sensors 0925-0950 S. Singh, J. Patterson, J. Burns and M. Dales Postscript rendering with virtual hardware 0950-1015 I. Hadzic and J.M. Smith P4: A platform for FPGA implementation of protocol boosters 1015-1115 Break and Poster Session E (parallel with Commercial Presentation V) M. Abramovici Satisfiability on reconfigurable hardware Y.I. El-Haffaf, A.K. Oudjida and A. Chohra Artificial digital neural network architecture for obstacle avoidance suitable for FPGAs T. Jebelean Auto-configurable array for GCD computation B. Laurent, G. Bosco and G. Saucier Structural versus algorithmic approaches for efficient adders on Xilinx 5200 FPGA 1045-1100 Commercial Presentation V: Virtual Computer Corporation Session 10: Control and Robotics 1115-1140 A. Tisserand FPGA implementation of real-time digital controllers using on-line arithmetic 1140-1205 T. Hollstein, A. Kirschbaum and M. Glesner A prototyping environment for fuzzy controllers 1205-1230 K. Nukata, Y. Shibata, H. Amano and Y. Anzai A reconfigurable sensor-data processing system for personal robots 1230-1240 Closing Remarks