CPU Registers

Table: MIPS registers and the convention governing their use.
Register Name Number Usage
zero 0 Constant 0
at 1 Reserved for assembler
v0 2 Expression evaluation and
v1 3 results of a function
a0 4 Argument 1
a1 5 Argument 2
a2 6 Argument 3
a3 7 Argument 4
t0 8 Temporary (not preserved across call)
t1 9 Temporary (not preserved across call)
t2 10 Temporary (not preserved across call)
t3 11 Temporary (not preserved across call)
t4 12 Temporary (not preserved across call)
t5 13 Temporary (not preserved across call)
t6 14 Temporary (not preserved across call)
t7 15 Temporary (not preserved across call)
s0 16 Saved temporary (preserved across call)
s1 17 Saved temporary (preserved across call)
s2 18 Saved temporary (preserved across call)
s3 19 Saved temporary (preserved across call)
s4 20 Saved temporary (preserved across call)
s5 21 Saved temporary (preserved across call)
s6 22 Saved temporary (preserved across call)
s7 23 Saved temporary (preserved across call)
t8 24 Temporary (not preserved across call)
t9 25 Temporary (not preserved across call)
k0 26 Reserved for OS kernel
k1 27 Reserved for OS kernel
gp 28 Pointer to global area
sp 29 Stack pointer
fp or s8 30 Frame pointer
ra 31 Return address (used by function call)

The MIPS (and SPIM) central processing unit contains 32 general purpose 32-bit registers that are numbered 0-31. Register $n$ is designated by $n. Register $0 always contains the hardwired value 0. MIPS has established a set of conventions as to how registers should be used. These suggestions are guidelines, which are not enforced by the hardware. However a program that violates them will not work properly with other software. Table [*] lists the registers and describes their intended use.

Registers $at (1), $k0 (26), and $k1 (27) are reserved for use by the assembler and operating system.

Registers $a0-$a3 (4-7) are used to pass the first four arguments to routines (remaining arguments are passed on the stack). Registers $v0 and $v1 (2, 3) are used to return values from functions. Registers $t0-$t9 (8-15, 24, 25) are caller-saved registers used for temporary quantities that do not need to be preserved across calls. Registers $s0-$s7 (16-23) are callee-saved registers that hold long-lived values that should be preserved across calls.

Register $sp (29) is the stack pointer, which points to the last location in use on the stack.4 Register $fp (30) is the frame pointer.5 Register $ra (31) is written with the return address for a call by the jal instruction.

Register $gp (28) is a global pointer that points into the middle of a 64K block of memory in the heap that holds constants and global variables. The objects in this heap can be quickly accessed with a single load or store instruction.

In addition, coprocessor 0 contains registers that are useful to handle exceptions. SPIM does not implement all of these registers, since they are not of much use in a simulator or are part of the memory system, which is not implemented. However, it does provide the following:

Register Name Number Usage
BadVAddr 8 Memory address at which address exception occurred
Status 12 Interrupt mask and enable bits
Cause 13 Exception type and pending interrupt bits
EPC 14 Address of instruction that caused exception
These registers are part of coprocessor 0's register set and are accessed by the lwc0, mfc0, mtc0, and swc0 instructions.

Figure: The Status register.
Figure: The Cause register.
Figure [*] describes the bits in the Status register that are implemented by SPIM. The interrupt mask contains a bit for each of the eight interrupt levels. If a bit is one, interrupts at that level are allowed. If the bit is zero, interrupts at that level are disabled. The low six bits of the Status register implement a three-level stack for the kernel/user and interrupt enable bits. The kernel/user bit is 0 if the program was running in the kernel when the interrupt occurred and 1 if it was in user mode. If the interrupt enable bit is 1, interrupts are allowed. If it is 0, they are disabled. At an interrupt, these six bits are shifted left by two bits, so the current bits become the previous bits and the previous bits become the old bits. The current bits are both set to 0 (i.e., kernel mode with interrupts disabled).

Figure [*] describes the bits in the Cause register. The eight pending interrupt bits correspond to the eight interrupt levels. A bit becomes 1 when an interrupt at its level has occurred but has not been serviced. The exception code bits contain a code from the following table describing the cause of an exception.

Number Name Description
0 INT External interrupt
4 ADDRL Address error exception (load or instruction fetch)
5 ADDRS Address error exception (store)
6 IBUS Bus error on instruction fetch
7 DBUS Bus error on data load or store
8 SYSCALL Syscall exception
9 BKPT Breakpoint exception
10 RI Reserved instruction exception
12 OVF Arithmetic overflow exception

Ian Moor 2009-03-11