Memory system

• The chip includes a 20KB instruction cache (32-bit block, 5-way set-associative) and a 16KB data cache (32-bit block, 4-way set-associative).
• The system includes a unified direct-mapped write-back 1MB secondary cache with 4-word cache blocks.
• Note that the matrix occupies  2MB.
• Each row of the matrix occupies  4KB.