Next: ... Up: Pipelining Previous: Pipelining

...

The basic idea :
Inst$^{\rm n}$                           
1  IF ID EX MEM WB                

2

    IF ID EX MEM WB              

3

      IF ID EX MEM WB            

4

        IF ID EX MEM WB          

5

          IF ID EX MEM WB        
Cycle  1 2 3 4 5 6 7 8 9

       
On each clock cycle another instruction is fetched and begins its five-step execution. Each instruction is completed five cycles later.

The CPI is now 1.

next up previous
Next: ... Up: Pipelining Previous: Pipelining