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Data hazards
Data hazards occur when the order of access to operands is changed by the introduction of pipelining.

Example:

ADD R1, R2, R3    (R1:=R2+R3)
SUB R4, R1, R5    (R4:=R1-R5)

Inst $^{\rm n}$

ADD R1,R2,R3 IF ID EX MEM WB

SUB R4,R1,R5 IF ID EX MEM WB

Cycle 1 2 3 4 5 6

$^\uparrow$ R1 written here

$^\uparrow$ R1 read here

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