Bypassing to avoid stalls

Recall the example:

ADD R1, R2, R3    (R1:=R2+R3)
SUB R4, R1, R5    (R4:=R1-R5)

Inst$^{\rm n}$

ADD R1,R2,R3

IF

ID

EX

MEM

WB

SUB R4,R1,R5

IF

ID

EX

MEM

WB

Cycle

1

2

3

4

5

6

$^\uparrow$R1 written here

$^\uparrow$R1 read here

• Because of pipelining, sequence of events no longer coincides with the data dependence.

• However, if we examine this example more carefully, it is apparent that the value is in fact calculated in time - it just isn't in the register yet.

 (H&P pp.147)