Bypassing multiple stages

ADD R1,R2,R3

IF

ID

EX$_\searrow$

MEM

WB

SUB R4,R1,R5

IF

ID

MEM

WB

AND R6,R1,R7

IF

ID

MEM

WB

OR R8,R1,R9

IF

ID

MEM

WB

XOR R10,R1,R11

IF

ID

EX

MEM

WB

Cycle

1

2

3

4

5

6

7

8

9

$^\uparrow$Forward to ADD as before

$^\uparrow$Forward to AND

$^\uparrow$No forwarding

• The AND instruction would stall unless the result of the ADD is forwarded -- but after one cycle delay
• The XOR needs no forwarding because its ID is after the ADD's WB has completed
• In the H&P DLX design, the OR requires no forwarding: the ADD's WB completes in the first half of the cycle, the OR's ID takes place in the second half.