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Up: Pipelining: avoiding stalls
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EXAMPLE:
LW R1,32(R6) |
| IF |
ID |
EX |
MEM |
WB |
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ADD R4,R1,R7 |
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IF |
ID |
 |
MEM.....
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SUB R5,R1,R8 |
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IF |
ID |
...... |
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AND R6,R1,R7 |
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IF |
ID |
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Cycle |
| 1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
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ADD not OK |
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SUB OK |
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It is not possible for the ADD to proceed since it needs the value
being read from memory at the beginning of the MEM cycle which will
fetch it.
Next: ...
Up: Pipelining: avoiding stalls
Previous: BYPASS TO MULTIPLE DESTINATIONS