Up: Average memory access time
Previous: ...
- SRAM is much faster than DRAM but too expensive
and power-hungry for bulk storage
- Caches rely on spatial and temporal locality
- Design variables: capacity, associativity,
block size, replacement policy and many more
- Write-through vs write-back
- Cache misses due to the three C's:
Compulsory, Capacity, Conflict
- Average memory access time (AMAT) depends
on applications's access pattern,
hit time, miss rate, miss penalty