Memory price/performance

• Dynamic RAM (DRAM):
  • Square array, one transistor per bit, data stored as charge on capacitor
  • Very low power
  • Discharge to read, so must write back -- so cycle time > access time
  • Charge slowly decays so needs periodic refresh
  • Address passed in two halves:
    • Row address (RAS) transfers data from a whole row into an on-chip buffer
    • Column address (CAS) selects required bit from buffer
    • Can issue one RAS then use many different CAS's to access the row buffer
  • Access time: ca.50ns (10-50 cycles)
  • Cycle time: ca.90ns
  • Commonly 64Mbit/chip or more
  • Various higher-performance interfaces available (SDRAM, RamBus, VDRAM)