Memory Hierarchies

Diagrams/hierarchy.eps

• Use a small amount of fast, expensive memory, backed up by a large amount of slower, cheaper memory which is large enough to store all data

• If an instruction refers to a datum which is not in the cache, it is automatically copied from the slow memory into the cache

• If most accesses can be satisfied by the cache, the average latency of memory accesses will be close to the cycle time of the cache

• We aim to achieve the performance of SRAM (expensive, fast) by using DRAM (cheaper, slower)