Advanced Computer
Architecture, Imperial College 2001
10
Multiple caches… and trouble
•Suppose processor 0 loads memory
location x
•x is
fetched from main memory and allocated into processor 0’s cache(s) First-level cache
x
CPU
second-level cache
x
First-level cache
CPU
second-level cache
First-level cache
CPU
second-level cache
Interconnection network
Main memory
x
Processor 0
Processor 1
Processor 2