Advanced Computer
Architecture, Imperial College 2001
12
Multiple caches… and trouble
•Suppose
processor 0 stores to memory location x
•Processor
0’s cached copy of x is updated
•Processor
1 continues to used the old value of x
First-level cache
x
CPU
second-level cache
x
First-level cache
x
CPU
second-level cache
x
First-level cache
CPU
second-level cache
Interconnection network
Main memory
x
Processor 0
Processor 1
Processor 2