Advanced Computer
Architecture, Imperial College 2001
13
Multiple caches… and trouble
•Suppose
processor 2 loads memory location x
•How does it know
whether to get x from main memory, processor 0 or processor 1?
First-level cache
x
CPU
second-level cache
x
First-level cache
x
CPU
second-level cache
x
First-level cache
X?
CPU
second-level cache
Interconnection network
Main memory
x
Processor 0
Processor 1
Processor 2