Advanced Computer Architecture

Chapter 7: shared memory and
cache consistency

Overview

Why add another processor?

Architectural effectiveness of Intel processors

Architectural effectiveness of Intel processors

Architectural effectiveness of Intel processors

How to add another processor?

How to add another processor?

How to connect processors...

Multiple caches… and trouble

Multiple caches… and trouble

Multiple caches… and trouble

Multiple caches… and trouble

Implementing distributed, shared memory

Cache consistency (aka cache coherency)

Implementing Strong Consistency: update

Implementing Strong Consistency: update…

A more cunning plan… invalidation

Update vs invalidate

The “Berkeley" Protocol

Berkeley cache coherence protocol:
state transition diagram

The job of the cache controller - snooping

Berkeley protocol - summary

Large-Scale Shared-Memory Multiprocessors

Case study:
Sun’s S3MP

S3MP: Read Requests

S3MP: Read Requests - remote

S3MP - Writes

S3MP - Replacements

Finding your data

ccNUMA summary

Beyond ccNUMA

Clustered architectures

Which cache should the cache controller control?

Summary and Conclusions