|
|
|
| Main memory |
||
| x |
||
| Interconnection
network |
| CPU |
| Processor 1 |
| Processor 2 |
| Processor 0 |
|
|
|
|
|
| • | Suppose
processor 1 loads memory location x |
|||
| • | x is fetched from main memory and allocated into |
|||
| processor
1’s cache(s) as well |
||||