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| • | Idea: systems linked by network connected via I/O bus |
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| – | Eg
Fujitsu AP3000, Myrinet, Quadrics |
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| • | Idea: CPU/memory packages linked by network connecting
main memory |
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| units |
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| – | Eg
SGI Origin |
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| • | Idea: CPUs share main memory |
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| – | Eg
Intel Xeon SMP (and many others) |
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| • | Idea: CPUs share L2/L3 cache |
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| – | Eg
IBM Power4 |
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| • | Idea: CPUs share L1 cache |
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| • | Idea: CPUs share registers, functional units |
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| – | Alpha
21464/EV8, Cray/Tera MTA (multithreaded architecture) |
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| • | Cunning Idea: do (almost) all the above
at the same time |
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| • | Eg IBM SP/Power4: 2 CPUs/chip sharing L2,
multichip module |
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| packages/links
4 chips/node, with L3 and DRAM for each CPU |
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| on
same board, with high-speed (ccNUMA) link to other nodes |
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| (see http://www.rs6000.ibm.com/resource/features/1999/power4.html) |
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