 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| • |
S3MP’s
cache coherency protocol implements strong
|
|
|
consistency
|
|
|
|
– |
Many
recent designs implement a weaker consistency
|
|
|
model…
|
|
|
| • |
S3MP
uses a singly-linked sharing chain
|
|
|
|
– |
Widely-shared
data – long chains – long invalidations, nasty
|
|
replacements
|
|
|
|
– |
“Widely
shared data is rare”
|
|
|
| • |
In
real life:
|
|
|
|
– |
IEEE
Scalable Coherent Interconnect (SCI): doubly-linked
|
|
|
sharing
list
|
|
|
|
– |
SGI
Origin 2000: bit vector sharing list
|
|
|
|
• |
Real
Origin 2000 systems in service with 256 CPUs
|
|
|
|
– |
Sun
E10000: hybrid multiple buses for invalidations,
|
|
|
separate
switched network for data transfers
|
|
|
|
• |
Many
E10000s in service, often with 64 CPUs
|
|
