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• |
L1
cache is already very busy with CPU traffic
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• |
L2
cache also very busy…
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• |
L3
cache doesn’t always have the current value for a
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cache
line
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1. |
Although
L1 cache is normally write-through, L2 is
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normally
write-back
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2. |
Some
data may bypass L3 (and perhaps L2) cache (eg
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when
stream-prefetched)
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– |
In
Power4, cache controller manages L2 cache – all
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external
invalidations/requests
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– |
L3
cache improves access to DRAM for accesses
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both
from CPU and from network
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