ACO-based Peak Power Estimation in VLSI Circuits


Estimation of maximum power consumption is an essential task in VLSI circuit realization since power value significantly affects the reliability of the circuits. The key issue of this problem is which pattern pair causes this peak power value. An exhaustive search from all possible combinations is time-consuming and impractical for VLSI circuits with hundreds of inputs. In this paper, one new method with Ant Colony Optimization (ACO), which imitates the behavior of ants looking for foods, is proposed for peak power estimation. The approach returns the patterns which are highly suspicious to consuming the peak power. These generated patterns are then applied into a commercial power calculation tool, PrimePower, for actual power calculation under the TSMC 0.18 um library. The gate delay issue and the valid state issue in sequential circuits are also considered in this paper. The experimental results show that an average of 76% tighter lower bound for the ISCAS’85 combinational benchmarks and 52% for the ISCAS’89 sequential circuits are obtained as compared to random patterns.

19th VLSI Design/CAD Symposium
Hualien, Taiwan

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