Zhiqiang (Walkie) Que

Huxley Building,
Department of Computing,
Imperial College London,
London, UK, SW7 2BZ
Email: z.<surname>@imperial.ac.uk

Work and Education Experience

  • Research Assistant, 2018 - present, Computing Department, Imperial College London, UK.

  • FPGA Specialist, 2015 - 2018, China Financial Futures Exchange (CFFEX) , China.
      I was the team leader to design and implement 1) the FPGA-based Low latency TCP/IP, UDP and Feima protocal hardened IPs and 2) the low latency trade and market data processing systems in China Financial Futures Exchange (CFFEX).

  • Senior Engineer, 2013 - 2015, Marvell Semiconductor, Shanghai, China.
    Engineer, 2012 - 2013, Marvell Semiconductor, Shanghai, China.
    Engineer, 2011 - 2012, Marvell Semiconductor, Chandler, AZ, USA.
      I worked on Micro-Architecture (ALU/Load/Store) design and verification of ARM-compliant CPUs.

  • Part-time engineer, 2008 - 2011, Xilinx University Program, Shanghai, China.
      I worked on many FPGA projects including NetFPGA, OpenSPARC, PetaLinux, DSP-Primer, BEE3, etc.

  • M.S., 2008 - 2011, CS, Shanghai Jiao Tong University (SJTU), Shanghai, China.

  • B.S., 2004 - 2008, Microelectronics, SJTU, Shanghai, China.

Awards & Scholarship

  • Outstanding Graduate Award, SJTU, 2011.
  • National Scholarship issued by Ministry of Education of the People's Republic of China, 2007.
  • Excellent Academic Scholarship, STJU, 2005, 2006 and 2007.
  • OOCL Scholarship, 2005.